AiP74LVC1G80

AiP74LV1T02는 단일 레벨 변환 기능을 갖춘 2입력 NOR 게이트입니다.낮은 임계값 입력은 VCC=3.3V에서 1.8V 입력 로직을 지원하며 1.8V에서 3.3V 레벨 업 변환에 사용할 수 있습니다.

The AiP74LV1T00 is a single, level translating 2-input NAND gate

The AiP74LVC1G00 provides the single 2-input NAND function. Input can be driven from either 3.3V or 5V devices. These features allow the use of these devices in a mixed 3.3V and 5V environment.

The AiP74LVC1G02 provides the single 2-input NOR function. Input can be driven from either 3.3V or 5V devices. These features allow the use of these devices in a mixed 3.3V and 5V environment.

The AiP74LVC1G04 provides one inverting buffer. Input can be driven from either 3.3V or 5V devices. These features allow the use of these devices in a mixed 3.3V and 5V environment.

The AiP74LVC1GU04 is a single unbuffered inverter. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC1G06 provides the inverting buffer. Input can be driven from either 3.3V or 5V devices. These features allow the use of these devices in a mixed 3.3V and 5V environment. The output of the device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.

The AiP74LVC1G07 provides the non-inverting buffer. The output of this device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC1G08 provides one 2-input AND function. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in mixed 3.3V and 5V applications.

The AiP74LVC1G10 provides a low-power, low-voltage single 3-input NAND gate.The inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.This device is fully specified for partial power-down applications using IOFF.The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

The AiP74LVC1G11 provides a single 3-input AND gate. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC1G14 provides the inverting buffer function with Schmitt-trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment. Schmitt-trigger action at the input makes the circuit tolerant for slower input rise and fall time. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

The AiP74LVC1G16 provides a low-power, low-voltage single buffer. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC1G18 is a 1-of-2 non-inverting demultiplexer with a 3-state output. The device buffers the data on input pin A and passes it either to output 1Y or 2Y, depending on whether the state of the select input (pin S) is LOW or HIGH. Input can be driven from either 3.3 or 5V devices. These features allow the use of these devices in a mixed 3.3 and 5V environment.

The AiP74LVC1G19 is a 1-of-2 decoder/demultiplexer with a common output enable. This device buffers the data on input A and passes it to the outputs 1Y (true) and 2Y (complement) when the enable (E(—)) input signal is LOW. Inputs can be driven from either 3.3V or 5V devices. These features allow the use of these devices in a mixed 3.3V and 5V environment.

The AiP74LVC1G27 provides one 3-input NOR function. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in mixed 3.3V and 5V applications.

The AiP74LVC1G32 provides one 2-input OR function. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in mixed 3.3V and 5V applications.

AiP74LV1T04는 단일 레벨 변환 반전 버퍼입니다. 낮은 임계값 입력은 1.8V를 지원합니다.VCC=3.3V에서의 입력 로직을 지원하며 1.8V에서 3.3V로 레벨업 변환에 사용할 수 있습니다. 또한 5V 내성을 갖습니다.입력 핀은 레벨 다운 변환(VCC=2.5V에서 3.3V를 2.5V 출력으로 변환)을 활성화합니다. 출력 레벨은 기준 전압을 사용합니다.공급 전압에 따라 작동하며 1.8V, 2.5V, 3.3V 및 5.0V CMOS 레벨을 지원합니다.

The AiP74LVC1G34 provides a low-power, low-voltage single buffer. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

AiP74LV1T08은 단일 레벨 변환 기능을 갖춘 2입력 AND 게이트입니다. 낮은 문턱 전압을 가진 입력은 VCC=3.3V에서 1.8V 입력 로직을 지원하며, 1.8V에서 3.3V로의 레벨 업 변환에 사용할 수 있습니다. 또한, 5V 내성 입력 핀을 통해 레벨 다운 변환(VCC=2.5V에서 3.3V에서 2.5V 출력)도 가능합니다. 출력 레벨은 공급 전압을 기준으로 하며 1.8V, 2.5V, 3.3V 및 5.0V CMOS 레벨을 지원합니다. 넓은 VCC 범위 덕분에 컨트롤러 또는 프로세서에 연결할 수 있는 다양한 출력 레벨을 생성할 수 있습니다.

The AiP74LVC1G38 provides a 2-input NAND function. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as translator in a mixed 3.3V and 5V environment.

AiP74LV1T32는 단일 레벨 변환 기능을 갖춘 2입력 OR 게이트입니다. 낮은 문턱 전압을 가진 입력은 VCC=3.3V에서 1.8V 입력 로직을 지원하며, 1.8V에서 3.3V로의 레벨 업 변환에 사용할 수 있습니다. 또한, 5V 내성 입력 핀을 통해 레벨 다운 변환(VCC=2.5V에서 3.3V에서 2.5V 출력)도 가능합니다. 출력 레벨은 공급 전압을 기준으로 하며 1.8V, 2.5V, 3.3V 및 5.0V CMOS 레벨을 지원합니다.

The AiP74LVC1G57 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer. All inputs can be connected to VCC or GND. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. All inputs (A, B and C) are Schmitt trigger inputs. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.

AiP74LV1T34는 단일 레벨 변환 버퍼입니다. 낮은 임계값 입력은 VCC=3.3V에서 1.8V 입력 로직을 지원하며 1.8V에서 3.3V로 레벨 업 변환에 사용할 수 있습니다. 또한 5V 내성 입력 핀은 레벨 다운 변환(VCC=2.5V에서 3.3V에서 2.5V 출력)을 가능하게 합니다. 출력 레벨은 공급 전압을 기준으로 하며 1.8V, 2.5V, 3.3V 및 5.0V CMOS 레벨을 지원합니다. 넓은 VCC 범위 덕분에 컨트롤러 또는 프로세서에 연결할 수 있는 다양한 출력 레벨을 생성할 수 있습니다.

The AiP74LVC1G58 provides configurable multiple functions.The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment

AiP74LV1T86은 단일 레벨 변환 기능을 갖춘 2입력 XOR 게이트입니다.낮은 문턱 전압을 갖는 입력은 VCC=3.3V에서 1.8V 입력 로직을 지원하며 1.8V에서 3.3V 레벨 업 범위에서 사용할 수 있습니다.또한, 5V 내성 입력 핀을 통해 레벨 다운 변환(3.3V에서 2.5V 출력)이 가능합니다.VCC=2.5V). 출력 레벨은 공급 전압을 기준으로 하며 1.8V, 2.5V, 3.3V 및 5.0V를 지원합니다.CMOS 레벨

The AiP74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (S(—)D) and reset (R(—)D) inputs, and complementary Q and Q(—) outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

AiP74LV1T87은 단일 레벨 변환 기능을 갖춘 2입력 EXCLUSIVE-NOR 게이트입니다. 낮은 문턱 전압을 가진 입력은 VCC=3.3V에서 1.8V 입력 로직을 지원하며, 1.8V에서 3.3V로의 레벨 업 변환에 사용할 수 있습니다. 또한, 5V 내성 입력 핀을 통해 레벨 다운 변환(VCC=2.5V에서 3.3V에서 2.5V 출력)도 가능합니다. 출력 레벨은 공급 전압을 기준으로 하며 1.8V, 2.5V, 3.3V 및 5.0V CMOS 레벨을 지원합니다.

The AiP74LVC1G79 provides a single positive-edge triggered D-type flip-flop.  Information on the data input is transferred to the Q-output on the LOW-to-HIGH transition of the clock pulse. The D-input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

AiP74LV1T125는 3상태 출력을 갖춘 단일 레벨 변환 버퍼/라인 드라이버입니다.

The AiP74LVC1G80 provides a single positive-edge triggered D-type flip-flop.  The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a  mixed 3.3V and 5V environment.

AiP74LV1T126은 3상태 출력을 갖춘 단일 레벨 변환 버퍼/라인 드라이버입니다.낮은 문턱 전압을 갖는 입력은 VCC=3.3V에서 1.8V 입력 로직을 지원하며 1.8V에서 3.3V 레벨 업 범위에서 사용할 수 있습니다.또한, 5V 내성 입력 핀을 통해 레벨 다운 변환(3.3V에서 2.5V 출력)이 가능합니다.VCC=2.5V). 출력 레벨은 공급 전압을 기준으로 하며 1.8V, 2.5V, 3.3V 및 5.0V를 지원합니다.CMOS 레벨

The AiP74LVC1G86 provides the 2-input EXCLUSIVE-OR function. Inputs can be driven from either 3.3V or 5V devices. These features allow the use of these devices in a mixed 3.3V and 5V environment.

AiP74LV4T125는 3상 출력을 갖는 쿼드 변환 버퍼/라인 드라이버입니다. 입력은 VCC=3.3V에서 1.8V 입력 로직에 맞춰 낮은 임계값 회로로 설계되어 1.8V에서 3.3V로 레벨업 변환에 사용할 수 있습니다. 또한, 5V 내성 입력 핀을 통해 다운 변환(예: VCC=2.5V에서 3.3V를 2.5V로 출력)도 가능합니다. 1.8V~5.5V의 넓은 VCC 범위는 컨트롤러 또는 프로세서에 연결하기 위한 원하는 출력 레벨을 생성할 수 있도록 해줍니다.

The 74LVC1G97 is a configurable multiple function gate with Schmitt-trigger inputs.  The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC1G98 is a configurable multiple function gate with Schmitt-trigger inputs.The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment

The AiP74LVC1G99 provides a low voltage, ultra-configurable, multiple function gate with 3-state  output. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a  mixed 3.3V and 5V environment.

The AiP74LVC1G123B is a single retriggerable monostable multivibrator with Schmitt trigger inputs. Output pulse width is controlled by three methods: 1. The basic pulse is programmed by selection of an external resistor (REXT) and capacitor (CEXT). 2. Once triggered, the basic output pulse width may be extended by retriggering the gated active LOW-going edge input ( ) or the active HIGH-going edge input (B). By repeating this process, the output pulse period (Q = HIGH) can be made as long as desired.  3. An internal connection from  to the input gates makes it possible to trigger the circuit by a HIGH-going signal at input .

The AiP74LVC1G125 provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE(—)). A HIGH-level at pin OE(—) causes the output to assume a high-impedance OFF-state. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC1G126 provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE). A LOW-level at pin OE causes the output to assume a high-impedance OFF-state. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC1G132 provides a dual 2-input NAND gate with schmitt-trigger inputs.The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC1G157 is a single 2-input multiplexer which select data from two data inputs (I0 and I1) under control of a common data select input (S). The state of the common data select input determines the particular register from which the data comes. The output (Y) presents the selected data in the true (non-inverted) form. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in mixed 3.3V and 5V applications.

The AiP74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The input can bedriven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC1G240 is a single line driver with a 3-state output. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC1G332 provides single 3-input OR gate. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC1G373 provides a D-type latch with 3-state output. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC1G374 provides a D-type flip-flop with 3-state output. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC1G386 provides a 3-input EXCLUSIVE-OR function. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC2G00 provides a 2-input NAND gate function. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V and 5V environment.

The AiP74LVC2G02 provides a 2-input NOR gate function. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V and 5V environment.

The AiP74LVC2G04 provides the dual inverting buffer. Inputs can be driven from either 3.3V or 5V devices. These features allow the use of these devices in a mixed 3.3V and 5V environment.

The AiP74LVC2GU04 provides two unbuffered inverters. Each inverter is a single stage with unbuffered output. The inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC2G06 provides two inverting buffers. The output of this device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

The AiP74LVC2G07 provides two non-inverting buffers. The output of this device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC2G08 provides a 2-input AND gate function. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of the AiP74LVC2G08 as a translator in a mixed 3.3V and 5V environment.

The AiP74LVC2G14 provides two inverting buffers with Schmitt-trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. The inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment. Schmitt-trigger action at the inputs makes the circuit tolerant of slower input rise and fall time.

The AiP74LVC2G16 provides two buffers. Inputs can be driven from either 3.3V or 5V devices. These features allow the use of these devices in a mixed 3.3V and 5V environment.

The AiP74LVC2G17 provides two non-inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V and 5V environment.

The AiP74LVC2G32 provides a 2-input OR gate function. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V and 5V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

The AiP74LVC2G34 provides two buffers. Inputs can be driven from either 3.3V or 5V devices. These features allow the use of these devices in a mixed 3.3V and 5V environment.

The AiP74LVC2G38 provides dual 2-input NAND function.  Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as  translators in a mixed 3.3V and 5V environment.

The AiP74LVC2G74 is a single positive-edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (S(—)D) and reset (R(—)D) inputs, and complementary Q and Q(—) outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable, one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

The AiP74LVC2G79 provides dual positive-edge triggered D-type flip-flop. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in mixed 3.3V and 5V applications.

The AiP74LVC2G86 provides a dual 2-input EXCLUSIVE-OR gate. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V and 5V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

The AiP74LVC2G125 provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (pin nOE(—)). A HIGH-level at pin nOE(—) causes the output to assume a high-impedance OFF-state.

The AiP74LVC2G126 is a dual non-inverting buffer/line driver with 3-state outputs. Each 3-state output is controlled by an output enable input (pin nOE). A LOW-level at pin nOE causes the output to assume a high-impedance OFF-state.  Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of the AiP74LVC2G126 as a translator in a mixed 3.3V and 5V environment.

The AiP74LVC1G132 provides a dual 2-input NAND gate with schmitt-trigger inputs.The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC2G157 is a single 2-line to 1-line data selector multiplexer which select data from two data inputs (A and B) under control of two common data inputs(A/B and G).  The input can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as  translators in mixed 3.3V and 5V applications.

The AiP74LVC2G240 is a dual inverting buffer/line driver with 3-state outputs.  The input can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as  translators in mixed 3.3V and 5V environment.

The AiP74LVC2G241 is a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. The input can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in mixed 3.3V and 5V applications.

The AiP74LVC3G04 provides three inverters. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC3GU04 is a triple unbuffered inverter. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC3G06 provides three inverters. The output of this device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND  functions. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC3G07 provides three non-inverting buffers. The output of this device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH  wired-AND functions. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC3G14 provides three inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. The inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment. Schmitt trigger action at the inputs makes the circuit tolerant of slower input rise and fall time. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

The AiP74LVC3G16 provides three buffers. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC3G17 provides three non-inverting buffers with Schmitt trigger input. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC3G34 provides three buffers. The inputs can be driven from either 3.3V or 5V devices. This feature allows the use of the AiP74LVC3G34 as a translator in a mixed 3.3V and 5V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

The AiP74LV00 provides a quad 2-input NAND function.

The AiP74LVC00 provides four 2-input NAND gates. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in mixed 3.3V and 5V applications.

The AiP74LV04 provides six inverting buffers.

The AiP74LVC04 provides six inverting buffers. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in mixed 3.3V and 5V applications.

The AiP74LVC07 provides six non-inverting buffers. The outputs are open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in mixed 3.3V and 5V applications.

The AiP74LV08 provides a quad 2-input AND function.

The AiP74LVC08 provides four 2-input AND gates. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in mixed 3.3V and 5V applications.

The AiP74LV14 is a low-voltage Si-gate CMOS device that is pin and function compatible with AiP74HC14 and AiP74HCT14. The AiP74LV14 provides six inverting buffers with Schmitt-trigger input. It is capable of transforming slowly-changing input signals into sharply defined, jitter-free output signals. The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.

The AiP74LVC14 provides six inverting buffers with Schmitt trigger input. It is capable of transforming slowly-changing input signals into sharply defined, jitter-free output signals.The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in mixed 3.3V and 5V applications.

The AiP74LVC17 provides six non-inverting buffers with Schmitt trigger input. It is capable of transforming slowly-changing input signals into sharply defined, jitter-free output signals.The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in mixed 3.3V and 5V applications.

The dual 4-input positive-AND gate is designed for 2V to 5.5V VCC operation.

The AiP74LV32 is a low-voltage CMOS device that is pin and function compatible with AiP74HC32 and AiP74HCT32. The AiP74LV32 provides a quad 2-input OR function.

The AiP74LVC32 provides four 2-input OR gates.Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in mixed 3.3V and 5V applications.

The AiP74LVC74 is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nS(—)D) and (nR(—)D) inputs, and complementary nQ and nQ(—) outputs.The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation.Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.

The AiP74LV125 is a low-voltage Si-gate CMOS device that is pin and function compatible with AiP74HC125 and AiP74HCT125. The AiP74LV125 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE—). A HIGH at nOE—causes the outputs to assume a high-impedance OFF-state

The AiP74LVC125 consists of four non-inverting buffers/line drivers with 3-state outputs (nY) that are controlled by the output enable input (nOE(—)). A HIGH at nOE(—)causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3V or 5V devices. When disabled, up to 5.5V can be applied to the outputs.

The AiP74LV126 is a low-voltage Si-gate CMOS device that is pin and function compatible with AiP74HC/HCT126. The AiP74LV126 consists of four non-inverting buffers/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A LOW at nOE causes the outputs to assume a high impedance OFF-state.

The AiP74LVC126 consists of four non-inverting buffers/line drivers with 3-state outputs, which are controlled by the output enable input (nOE). A LOW at nOE causes the outputs to assume a high-impedance OFF-state.Inputs can be driven from either 3.3V or 5V devices. When disabled, up to 5.5V can be applied to the outputs.

The AiP74LVC132 provides four 2-input NAND gates with Schmitt trigger inputs. It is capable of transforming slowly-changing input signals into sharply defined, jitter-free output signals.The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in mixed 3.3V and 5V environment.

The AiP74LVC138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive outputs (Y(—)0 to Y(—)7) that are LOW when selected.There are three enable inputs: two active LOW (E(—)1 and E(—)2) and one active HIGH (E3). Every output will be HIGH unless E(—)1 and E(—)2 are LOW and E3 is HIGH.This multiple enable function allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four AiP74LVC138 devices and one inverter. The AiP74LVC138 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state.

The AiP74LVC139 is a dual 2-to-4 line decoder/demultiplexer.. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC157 is a quad 2-input multiplexer which select four bits of data from two sources under the control of a common select input (S). The four outputs present the selected data in the true (non-inverted) form. The enable input (E(—)) is active LOW. When pin E(—) is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all the other input conditions. Moving the data from two groups of registers to four common output buses is a common use of the AiP74LVC157. The state of the common data select input (S) determines the particular register from which the data comes. It can also be used as function generator.It is useful for implementing highly irregular logic by generating any 4 of the 16 different functions of two variables with one variable common.The device is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to pin S.Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in mixed 3.3V and 5V applications.